Reducing conflicts in direct mapped caches

ABSTRACT

A processor includes a core to execute a transaction with a memory via cache; and cache controller having an index mapper circuit to: identify a physical memory address associated with the transaction and having a plurality of bits; determine, based on the plurality of bits, a first set of bits encoding a tag value, a second set of bits encoding a page index value, and a third set of bits encoding a line index value; determine a mapping function corresponding to the tag value; determine, using the mapping function, a bit-placement order; combine, based on the order, second and third set of bits to form an index; generate, using the index, a mapping from the address to a cache line index value identifying a cache line in the cache; and wherein the cache controller is further to access, using the mapping and in response to the transaction, the cache line.

RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No. 15/474,654, filed Mar. 30, 2017, now U.S. Pat. No. 10,296,457, issued May 21, 2019, the entirety of which is incorporated herein by reference.

TECHNICAL FIELD

The embodiments of the disclosure relate generally to memory management and, more specifically, to systems and methods that reduce conflicts in direct mapped caches such as memory-side caches.

BACKGROUND

Caches of a processor may be used to hold copies of data stored in memory in order to shorten the latency of subsequent accesses to the data by the processor. In some scenarios, caches may be shared by multiple hardware processing components associated with the processor. The caches may be used to temporarily store data both from memory-mapped input/output devices (MMIO), such as data from stored on a hard disk or in a basic input output system (BIOS) read only memory (ROM), as well as from random access memory (RAM).

BRIEF DESCRIPTION OF THE DRAWINGS

The disclosure will be understood more fully from the detailed description given below and from the accompanying drawings of various embodiments of the disclosure. The drawings, however, should not be taken to limit the disclosure to the specific embodiments, but are for explanation and understanding only.

FIG. 1 illustrates a processing system according to an embodiment of the present disclosure.

FIG. 2 illustrates an example of cache line index mapping according to an embodiment of the present disclosure.

FIG. 3A illustrates another mapping function according to an embodiment of the present disclosure.

FIG. 3B illustrates an index mapper circuit according to an embodiment of the present disclosure.

FIG. 4 is a block diagram of a method to generate a cache line index based on the tag value of a physical memory address according to an embodiment of the present disclosure.

FIG. 5A is a block diagram illustrating a micro-architecture for a processor including heterogeneous core in which one embodiment of the disclosure may be used.

FIG. 5B is a block diagram illustrating an in-order pipeline and a register renaming stage, out-of-order issue/execution pipeline implemented according to at least one embodiment of the disclosure.

FIG. 6 illustrates a block diagram of the micro-architecture for a processor that includes logic in accordance with one embodiment of the disclosure.

FIG. 7 is a block diagram illustrating a system in which an embodiment of the disclosure may be used.

FIG. 8 is a block diagram of a system in which an embodiment of the disclosure may operate.

FIG. 9 is a block diagram of a system in which an embodiment of the disclosure may operate.

FIG. 10 is a block diagram of a System-on-a-Chip (SoC) in accordance with an embodiment of the present disclosure

FIG. 11 is a block diagram of an embodiment of an SoC design in accordance with the present disclosure.

FIG. 12 illustrates a block diagram of one embodiment of a computer system.

DETAILED DESCRIPTION

The memory associated with a processor may include a tiered memory structure including a memory-side cache (MSC) and a far memory. The processor may be associated with a cache structure including level 1 to level 3 (L1-L3) caches and a last-level cache (LLC). The contents stored in a cache line of the LLC may be evicted to the MSC. The MSC can be a near memory (i.e., a memory that is close to a processor) that caches contents for a far memory (i.e., a memory that is farther away from the processor than the near memory), where the far memory is typically much larger than the near memory. For the purpose of concise description, the far memory is referred to as the “memory” hereafter.

The processor may execute a transaction using virtual memory addresses. A memory controller may translate the virtual memory address into a physical memory address that references a memory location. The memory may be organized according to memory pages (e.g., 4 kilobytes per page or 2 megabytes per page). Thus, a physical memory address may include an identifier of the memory page and an identifier of the lines to store references to memory locations within the memory page.

A cache line in the MSC may temporarily store a copy of content stored by a memory location referenced by a physical memory address. The processor can access content stored in the MSC quicker than the corresponding copy stored in the memory. Since the size of the memory is commonly much larger than the size of the MSC, the memory, in some implementations (e.g., the direct mapped cache scheme), may be divided into groups of memory addresses, where a portion of a memory address (e.g., bit 6-35) in a group can be mapped to a cache index value identifying the cache lines of the MSC. Thus, the physical memory address may contain a tag value (e.g., the most significant bits) to identify a memory address group. The number of memory address groups that are matched to the MSC may determine the number of bits encoding the tag value. For example, if the memory address space is divided into eight memory address groups (where each memory address group is mapped to the complete range of cache lines of the MSC), the tag value may be encoded using 3 bits.

The MSC, in practice, is commonly implemented as a direct mapped cache (DMC) to reduce access overheads. In a direct mapped cache, a memory location is uniquely associated with a cache line. The cache controller may calculate the cache line index value within the MSC based on the page index value and the line index value of the physical memory address. As discussed above, since the memory is much larger than the MSC, the cache controller may map multiple memory locations (e.g., memory locations associated with different memory address groups) to the same cache line under the DMC mapping scheme. When the processor executes a transaction with a physical memory address linked to a cache line that is already associated with another physical memory address, the cache controller needs to evict the cache line to make space for the contents of the physical memory address. This eviction is referred to as a cache conflict event that can trigger an eviction.

Because the operating system (due to constant allocation and de-allocation of memory pages) may fragment the memory, a direct mapped cache may encounter frequent cache conflicts. Further, the cache conflicts can concentrate around a spatial area in the direct mapped cache because adjacent cache lines are likely to be accessed in a single transaction. Thus, once the cache controller evicts a cache line in the MSC due to a cache conflict, the cache lines surrounding the conflicted cache line very likely also need to be evicted. Because MSC evictions may slow down the execution of a transaction, there is a need to reduce the number of cache conflicts in the direct mapped MSC. Embodiments of the present disclosure include a cache controller that reduces the number of cache conflicts by using different cache line mapping functions for different memory address groups.

FIG. 1 illustrates a processing system 100 according to an embodiment of the present disclosure. In one embodiment, the processing system 100 may be implemented as a system-on-a-chip (Soc). The processing system 100 may include a processor 102 (such as a CPU) and a two-level memory that may include a first level memory 104 (hereafter referred to as the memory-side cache due to its proximity to the processing core and being used as a cache for far memory) and a second level memory 106 (hereafter referred to as the far memory or the memory). In one embodiment, the first level memory may include volatile memory (such as volatile DRAM) implemented to function as a software-transparent memory-side cache 106. In another embodiment, the memory-side cache may be a last level cache (LLC) associated with the processor 102. The second level memory 106 may be software-visible. The processor 102, the memory-side cache 104, and the memory 106 are communicatively connected via an interconnect 108.

The processor 102 may include a processing core 110 and a memory-side cache controller 112 (hereafter referred to as “cache controller”). The processing core 110 may execute transactions with memory 106. In one embodiment, the memory-side cache 104 is implemented as a cache to memory 106. The memory-side cache 104 may temporarily store data relating to the transactions with memory 106. Cache controller 112 is a logic circuit that monitors the transactions with memory 106. In one embodiment, cache controller 112 may include an index mapper circuit 114 to convert a physical memory address to a cache line index value based on which processing core 110 may associate a cache line 116 with a physical memory location in memory 106.

As discussed above, memory-side cache 104 may be implemented as a direct mapped cache. Because memory 106 is larger than memory-side cache 104, the address space of memory 106 may be divided into groups of memory addresses (each including a number of memory pages) 118A-118D, where the memory locations in each memory address group are mapped to the cache lines in memory-side cache 104. A memory page number may be used to determine the memory address group to which the memory page belongs. Cache conflicts may occur because memory locations from different memory address groups 118A-118D may be mapped to the same cache line. In some implementations, cache controller 112 uses a common mapping function to convert physical memory addresses in different memory address groups to the cache line index values. Thus, the memory locations associated different memory address groups 118A-118D may be mapped to the cache line index values in a same sequential order. For example, cache controller 112 may map the memory locations sequentially (from low to high memory addresses) to cache line index values. The common mapping function for different memory address groups 118A-118D can cause the concentrated cache conflicts in memory-side cache 104 because memory locations in a same neighborhood of different memory address groups are mapped to a same neighborhood in the memory-side cache 104.

Embodiments of the present disclosure may employ different mapping functions for different memory address groups. In one embodiment, cache controller 112 may include an index mapper circuit 114 to use these different mapping functions to convert physical memory addresses of different memory address groups into cache line index values. Thus, memory locations in a memory address range associated with different memory address groups may be mapped to different address regions in the memory-side cache 104, resulting in a scattered cache line locations that may effectively reduce the number of cache conflicts associated with spatial locality.

In one embodiment, each mapping function is selected based on the tag value that identifies a memory address group in the physical memory address. Each mapping function may specify a unique order to associate the memory locations with cache lines in memory-side cache 104. Thus, physical memory addresses within a same memory address range in two different memory address groups (e.g., position 4 in 118A and 118B) may be mapped to two different cache line index values (e.g., 4 and 8). This, as shown in the example of FIG. 2, may help significantly reduce the number of cache conflicts.

The mapping functions according to embodiments of the present disclosure can be implemented in various manners as long as they can map two physical memory addresses in a same memory address range in two memory address groups to two different cache line index values. In one embodiment, the different mapping functions may be achieved by re-arranging the bit positions of cache line index values in different orders for different memory address groups. FIG. 2 illustrates an example 200 of cache line index mapping according to an embodiment of the present disclosure. As shown in FIG. 2, a physical memory address 202 may include a tag value 204, a page index value 206, and a line index value 208. Tag value 204 may identify the memory address group to which physical memory address 202 is associated with. For concise illustration, the example 200 as shown in FIG. 2 shows a memory-side cache 210 containing eight cache lines (A-H) and a memory 214 containing 24 memory locations (0-23). Thus, in a direct mapped cache, the memory locations are divided into three groups (Group 1, 2, 3), where each group includes two memory pages 212 (page 0, 1) that each includes references to four memory locations. In this example, tag value 204 may identify memory address groups 1-3.

Page index value 206 may identify the memory page to which the physical memory address belongs. For the convenience of illustration, index mapper circuit 114 may convert the page index value 206 into a relative page position within a memory address group. The relative page position may be a page index with respective to the lowest memory address of the memory address group. The relative position of the memory page in a memory address group can be represented using bits encoding the page index value 206. In this example 200, since each memory page is associated with four memory locations, each memory address group includes two memory pages as shown in column 212. The memory pages in a memory address group may be identified by one bit (X=0/1). The bit value may represent the relative position of the memory page in the group.

Similarly, line index value 208 may identify memory locations by their relative positions within a memory page as shown at column 214 of FIG. 2. In this example 200, each memory page includes four memory locations that can be identified using two bits (YZ) by their relative positions within a memory page. A mapping function can be constructed from the bits (X, Y, Z) encoding the page index value 206 and line index value 208 (e.g., mapping according to XYZ where X is the most significant bit and Z is the least significant bit). When different memory address groups are mapped according to a same mapping function (XYZ), the memory locations in each memory address groups are mapped to cache line indices A through H in the same sequential order. This identical mapping for different memory address groups can cause cache conflicts (with spatial locality) for all of the cache lines.

Index mapper circuit 114 of cache controller 112 in an embodiment may employ different mapping functions for different memory address groups. As shown in column 218 of FIG. 2, the different mapping functions can be achieved by permuting the order of bits encoding the page index value 206 (e.g., X is the bit used to encode the page index value) and line index value 208 (e.g., YZ are the two bits used to encode the line index value). The bits encoding the page index value and the line index values may be combined into a string of bits according to a bit-placement order that determines the position of a bit in the string of bits. Index mapper circuit 114 may first determine a bit-placement order for these bits (i.e., how to place X, Y, Z in the string of bits). The combination of these bits in the string according to the bit-placement order may form an index value that may be used to map from the physical memory address to a cache line index value. Because different memory address groups are associated with different index values, the mapping is not clustered. In this example, index mapper circuit 114 may employ a first mapping function (XYZ) to convert the physical memory addresses in memory address group one, a second mapping function (YXZ) to convert the physical memory addresses in memory address group two, and a third mapping function (ZYX) to convert the physical memory addresses in memory address group three. The same sequence of memory locations in these three groups is converted into cache line indices of (A, B, C, D, E, F, G, H), (A, B, E, F, C, D, G, H), and (A, E, C, G, B, F, D, H). Thus, the chance of cache conflicts with spatial locality is reduced by at least 50% because fewer than 50% neighboring memory locations are mapped to neighboring cache lines.

FIG. 3A illustrates another mapping function according to an embodiment of the present disclosure. In this embodiment, index mapper circuit 114 may first swap n bits starting from a bit position p in the page index value 304 with n bits starting from a bit position q in the line index value 306, where n, p, q are integers that equal to or are greater than one (1). Index mapper circuit 114 may choose different values of n, p, q based on different tag values 302. The values of n, p, q can be selected as a different combination for a different tag value. Index mapper circuit 114 may then calculate the cache line index values using bits stored in the page index value 304 and line index value 306 after the bit swapping. Thus, each memory address group is associated with a different mapping function. For example, cache line index values associated with the first memory address group as shown in FIG. 2 may be calculated by swapping one (1) bit starting at position one (1) of page index value 304 with one (1) bit starting at position one (1) of line index value 306; cache line index values associated with the second memory address group may be calculated by swapping two (2) bits starting at position one (1) of page index value 304 with two (2) bits starting at position one (1) of line index value 306; and cache line index values associated with the third memory address group may be calculated by swapping three (3) bits starting at position one (1) of page index value 304 with three (3) bits starting at position one (1) of line index value 306. Thus, same memory locations of different memory address groups may be mapped to different cache lines by the different mapping functions. In another embodiment, the number (n) of bits may be kept constant (e.g., n=2). The bit positions (p, q) may change for different memory address groups. For example, the first memory address group may start from bit position 1 (p=1, q=1); the second memory address group may start from bit position 2 (p=2, q=2), etc.

FIG. 3B illustrates an index mapper circuit 308 according to an embodiment of the present disclosure. In one embodiment, as shown in FIG. 3B, cache controller circuit 308 may include multiplexer circuits 310, 312. Each of multiplexer circuits 310, 312 may include a first input node to receive bits encoding page index value 304 and a second input node to receive bits encoding line index value 306. Each of multiplexer circuits 310, 312 may further include a control node to receive tag value 302. In one embodiment, each of multiplexer circuits 310, 312 may be reconfigured based on the tag value 302 received at the control node to enable bit swapping between page index value 304 and line index value 306. For example, as discussed in conjunction with FIG. 3A, multiplexer circuits 310, 312 may be reconfigured to allow one-bit, two-bits, or three-bit swapping depending on tag value 302, thus achieving different mapping functions for different memory address groups.

FIG. 4 is a block diagram of a method 400 to provide consistent updates to persistent memory according to an embodiment of the present disclosure. Method 400 may be performed by processing logic that may include hardware (e.g., circuitry, dedicated logic, programmable logic, microcode, etc.), software (such as instructions run on a processing device, a general purpose computer system, or a dedicated machine), firmware, or a combination thereof. In one embodiment, method 400 may be performed, in part, by processing logic circuits of the processor 102 including cache controller 112 and index mapper circuit 114 as shown in FIG. 1.

For simplicity of explanation, the method 400 is depicted and described as a series of acts. However, acts in accordance with this disclosure can occur in various orders and/or concurrently and with other acts not presented and described herein. Furthermore, not all illustrated acts may be performed to implement the method 400 in accordance with the disclosed subject matter. In addition, those skilled in the art will understand and appreciate that the method 400 could alternatively be represented as a series of interrelated states via a state diagram or events.

At 402, the processing logic may identify, by a processor, a physical memory address of a memory page, wherein the physical memory address comprises a plurality of bits.

At 404, the processing logic may determine, based on the plurality of bits, a first set of bits encoding a tag value, a second set of bits encoding a page index value, and a third set of bits encoding a line index value.

At 406, the processing logic may determine, based on the tag value, a bit-placement order for combining the second set of bits and the third set of bits.

At 408, the processing logic may combine, based on the bit-placement order, the second set of bits and the third set of bits to form an index.

At 410, the processing logic may generate, based on the index, a mapping from the physical memory address to a cache line index value identifying a cache line in the cache.

At 412, the processing logic may access, based on the mapping to the cache line, a memory location referenced by the physical memory address.

FIG. 5A is a block diagram illustrating a micro-architecture for a processor 500 that implements the processing device including heterogeneous cores in accordance with one embodiment of the disclosure. Specifically, processor 500 depicts an in-order architecture core and a register renaming logic, out-of-order issue/execution logic to be included in a processor according to at least one embodiment of the disclosure.

Processor 500 includes a front end unit 530 coupled to an execution engine unit 550, and both are coupled to a memory unit 570. The processor 500 may include a reduced instruction set computing (RISC) core, a complex instruction set computing (CISC) core, a very long instruction word (VLIW) core, or a hybrid or alternative core type. As yet another option, processor 500 may include a special-purpose core, such as, for example, a network or communication core, compression engine, graphics core, or the like. In one embodiment, processor 500 may be a multi-core processor or may part of a multi-processor system.

The front end unit 530 includes a branch prediction unit 532 coupled to an instruction cache unit 534, which is coupled to an instruction translation lookaside buffer (TLB) 536, which is coupled to an instruction fetch unit 538, which is coupled to a decode unit 540. The decode unit 540 (also known as a decoder) may decode instructions, and generate as an output one or more micro-operations, micro-code entry points, microinstructions, other instructions, or other control signals, which are decoded from, or which otherwise reflect, or are derived from, the original instructions. The decoder 540 may be implemented using various different mechanisms. Examples of suitable mechanisms include, but are not limited to, look-up tables, hardware implementations, programmable logic arrays (PLAs), microcode read only memories (ROMs), etc. The instruction cache unit 534 is further coupled to the memory unit 570. The decode unit 540 is coupled to a rename/allocator unit 552 in the execution engine unit 550.

The execution engine unit 550 includes the rename/allocator unit 552 coupled to a retirement unit 554 and a set of one or more scheduler unit(s) 556. The scheduler unit(s) 556 represents any number of different schedulers, including reservations stations (RS), central instruction window, etc. The scheduler unit(s) 556 is coupled to the physical register file(s) unit(s) 558. Each of the physical register file(s) units 558 represents one or more physical register files, different ones of which store one or more different data types, such as scalar integer, scalar floating point, packed integer, packed floating point, vector integer, vector floating point, etc., status (e.g., an instruction pointer that is the address of the next instruction to be executed), etc. The physical register file(s) unit(s) 558 is overlapped by the retirement unit 554 to illustrate various ways in which register renaming and out-of-order execution may be implemented (e.g., using a reorder buffer(s) and a retirement register file(s), using a future file(s), a history buffer(s), and a retirement register file(s); using a register maps and a pool of registers; etc.).

In one implementation, processor 500 may be the same as processor 102 described with respect to FIG. 1A.

Generally, the architectural registers are visible from the outside of the processor or from a programmer's perspective. The registers are not limited to any known particular type of circuit. Various different types of registers are suitable as long as they are capable of storing and providing data as described herein. Examples of suitable registers include, but are not limited to, dedicated physical registers, dynamically allocated physical registers using register renaming, combinations of dedicated and dynamically allocated physical registers, etc. The retirement unit 554 and the physical register file(s) unit(s) 558 are coupled to the execution cluster(s) 560. The execution cluster(s) 560 includes a set of one or more execution units 562 and a set of one or more memory access units 564. The execution units 562 may perform various operations (e.g., shifts, addition, subtraction, multiplication) and operate on various types of data (e.g., scalar floating point, packed integer, packed floating point, vector integer, vector floating point).

While some embodiments may include a number of execution units dedicated to specific functions or sets of functions, other embodiments may include only one execution unit or multiple execution units that all perform all functions. The scheduler unit(s) 556, physical register file(s) unit(s) 558, and execution cluster(s) 560 are shown as being possibly plural because certain embodiments create separate pipelines for certain types of data/operations (e.g., a scalar integer pipeline, a scalar floating point/packed integer/packed floating point/vector integer/vector floating point pipeline, and/or a memory access pipeline that each have their own scheduler unit, physical register file(s) unit, and/or execution cluster—and in the case of a separate memory access pipeline, certain embodiments are implemented in which only the execution cluster of this pipeline has the memory access unit(s) 564). It should also be understood that where separate pipelines are used, one or more of these pipelines may be out-of-order issue/execution and the rest in-order.

The set of memory access units 564 is coupled to the memory unit 570, which may include a data prefetcher 580, a data TLB unit 572, a data cache unit (DCU) 574, and a level 2 (L2) cache unit 576, to name a few examples. In some embodiments DCU 574 is also known as a first level data cache (L1 cache). The DCU 574 may handle multiple outstanding cache misses and continue to service incoming stores and loads. It also supports maintaining cache coherency. The data TLB unit 572 is a cache used to improve virtual address translation speed by mapping virtual and physical memory address spaces. In one exemplary embodiment, the memory access units 564 may include a load unit, a store address unit, and a store data unit, each of which is coupled to the data TLB unit 572 in the memory unit 570. The L2 cache unit 576 may be coupled to one or more other levels of cache and eventually to a main memory.

In one embodiment, the data prefetcher 580 speculatively loads/prefetches data to the DCU 574 by automatically predicting which data a program is about to consume. Prefeteching may refer to transferring data stored in one memory location of a memory hierarchy (e.g., lower level caches or memory) to a higher-level memory location that is closer (e.g., yields lower access latency) to the processor before the data is actually demanded by the processor. More specifically, prefetching may refer to the early retrieval of data from one of the lower level caches/memory to a data cache and/or prefetch buffer before the processor issues a demand for the specific data being returned.

The processor 500 may support one or more instructions sets (e.g., the x86 instruction set (with some extensions that have been added with newer versions); the MIPS instruction set of MIPS Technologies of Sunnyvale, Calif.; the ARM instruction set (with optional additional extensions such as NEON) of ARM Holdings of Sunnyvale, Calif.).

It should be understood that the core may support multithreading (executing two or more parallel sets of operations or threads), and may do so in a variety of ways including time sliced multithreading, simultaneous multithreading (where a single physical core provides a logical core for each of the threads that physical core is simultaneously multithreading), or a combination thereof (e.g., time sliced fetching and decoding and simultaneous multithreading thereafter such as in the Intel® Hyperthreading technology).

While register renaming is described in the context of out-of-order execution, it should be understood that register renaming may be used in an in-order architecture. While the illustrated embodiment of the processor also includes a separate instruction and data cache units and a shared L2 cache unit, alternative embodiments may have a single internal cache for both instructions and data, such as, for example, a Level 1 (L1) internal cache, or multiple levels of internal cache. In some embodiments, the system may include a combination of an internal cache and an external cache that is external to the core and/or the processor. Alternatively, all of the cache may be external to the core and/or the processor.

FIG. 5B is a block diagram illustrating an in-order pipeline and a register renaming stage, out-of-order issue/execution pipeline implemented by processing device 500 of FIG. 5A according to some embodiments of the disclosure. The solid lined boxes in FIG. 5B illustrate an in-order pipeline, while the dashed lined boxes illustrates a register renaming, out-of-order issue/execution pipeline. In FIG. 5B, a processor pipeline 500 includes a fetch stage 502, a length decode stage 504, a decode stage 506, an allocation stage 508, a renaming stage 510, a scheduling (also known as a dispatch or issue) stage 512, a register read/memory read stage 514, an execute stage 516, a write back/memory write stage 518, an exception handling stage 522, and a commit stage 524. In some embodiments, the ordering of stages 502-524 may be different than illustrated and are not limited to the specific ordering shown in FIG. 5B.

FIG. 6 illustrates a block diagram of the micro-architecture for a processor 600 that includes hybrid cores in accordance with one embodiment of the disclosure. In some embodiments, an instruction in accordance with one embodiment can be implemented to operate on data elements having sizes of byte, word, doubleword, quadword, etc., as well as datatypes, such as single and double precision integer and floating point datatypes. In one embodiment the in-order front end 601 is the part of the processor 600 that fetches instructions to be executed and prepares them to be used later in the processor pipeline.

The front end 601 may include several units. In one embodiment, the instruction prefetcher 626 fetches instructions from memory and feeds them to an instruction decoder 628 which in turn decodes or interprets them. For example, in one embodiment, the decoder decodes a received instruction into one or more operations called “micro-instructions” or “micro-operations” (also called micro op or uops) that the machine can execute. In other embodiments, the decoder parses the instruction into an opcode and corresponding data and control fields that are used by the micro-architecture to perform operations in accordance with one embodiment. In one embodiment, the trace cache 630 takes decoded uops and assembles them into program ordered sequences or traces in the uop queue 634 for execution. When the trace cache 630 encounters a complex instruction, the microcode ROM 632 provides the uops needed to complete the operation.

Some instructions are converted into a single micro-op, whereas others need several micro-ops to complete the full operation. In one embodiment, if more than four micro-ops are needed to complete an instruction, the decoder 628 accesses the microcode ROM 632 to do the instruction. For one embodiment, an instruction can be decoded into a small number of micro ops for processing at the instruction decoder 628. In another embodiment, an instruction can be stored within the microcode ROM 632 should a number of micro-ops be needed to accomplish the operation. The trace cache 630 refers to an entry point programmable logic array (PLA) to determine a correct micro-instruction pointer for reading the micro-code sequences to complete one or more instructions in accordance with one embodiment from the micro-code ROM 632. After the microcode ROM 632 finishes sequencing micro-ops for an instruction, the front end 601 of the machine resumes fetching micro-ops from the trace cache 630.

The out-of-order execution engine 603 is where the instructions are prepared for execution. The out-of-order execution logic has a number of buffers to smooth out and re-order the flow of instructions to optimize performance as they go down the pipeline and get scheduled for execution. The allocator logic allocates the machine buffers and resources that each uop needs in order to execute. The register renaming logic renames logic registers onto entries in a register file. The allocator also allocates an entry for each uop in one of the two uop queues, one for memory operations and one for non-memory operations, in front of the instruction schedulers: memory scheduler, fast scheduler 602, slow/general floating point scheduler 604, and simple floating point scheduler 606. The uop schedulers 602, 604, 606, determine when a uop is ready to execute based on the readiness of their dependent input register operand sources and the availability of the execution resources the uops need to complete their operation. The fast scheduler 602 of one embodiment can schedule on each half of the main clock cycle while the other schedulers can only schedule once per main processor clock cycle. The schedulers arbitrate for the dispatch ports to schedule uops for execution.

Register files 608, 610, sit between the schedulers 602, 604, 606, and the execution units 612, 614, 616, 618, 620, 622, 624 in the execution block 611. There is a separate register file 608, 610, for integer and floating point operations, respectively. Each register file 608, 610, of one embodiment also includes a bypass network that can bypass or forward just completed results that have not yet been written into the register file to new dependent uops. The integer register file 608 and the floating point register file 610 are also capable of communicating data with the other. For one embodiment, the integer register file 608 is split into two separate register files, one register file for the low order 32 bits of data and a second register file for the high order 32 bits of data. The floating point register file 610 of one embodiment has 128 bit wide entries because floating point instructions typically have operands from 64 to 128 bits in width.

The execution block 611 contains the execution units 612, 614, 616, 618, 620, 622, 624, where the instructions are actually executed. This section includes the register files 608, 610, that store the integer and floating point data operand values that the micro-instructions need to execute. The processor 600 of one embodiment is comprised of a number of execution units: address generation unit (AGU) 612, AGU 614, fast ALU 616, fast ALU 618, slow ALU 620, floating point ALU 622, floating point move unit 624. For one embodiment, the floating point execution blocks 622, 624, execute floating point, MMX, SIMD, and SSE, or other operations. The floating point ALU 622 of one embodiment includes a 64 bit by 64 bit floating point divider to execute divide, square root, and remainder micro-ops. For embodiments of the present disclosure, instructions involving a floating point value may be handled with the floating point hardware.

In one embodiment, the ALU operations go to the high-speed ALU execution units 616, 618. The fast ALUs 616, 618, of one embodiment can execute fast operations with an effective latency of half a clock cycle. For one embodiment, most complex integer operations go to the slow ALU 620 as the slow ALU 620 includes integer execution hardware for long latency type of operations, such as a multiplier, shifts, flag logic, and branch processing. Memory load/store operations are executed by the AGUs 612, 614. For one embodiment, the integer ALUs 616, 618, 620, are described in the context of performing integer operations on 64 bit data operands. In alternative embodiments, the ALUs 616, 618, 620, can be implemented to support a variety of data bits including 16, 32, 128, 256, etc. Similarly, the floating point units 622, 624, can be implemented to support a range of operands having bits of various widths. For one embodiment, the floating point units 622, 624, can operate on 128 bits wide packed data operands in conjunction with SIMD and multimedia instructions.

In one embodiment, the uops schedulers 602, 604, 606, dispatch dependent operations before the parent load has finished executing. As uops are speculatively scheduled and executed in processor 600, the processor 600 also includes logic to handle memory misses. If a data load misses in the data cache, there can be dependent operations in flight in the pipeline that have left the scheduler with temporarily incorrect data. A replay mechanism tracks and re-executes instructions that use incorrect data. Only the dependent operations need to be replayed and the independent ones are allowed to complete. The schedulers and replay mechanism of one embodiment of a processor are also designed to catch instruction sequences for text string comparison operations.

The processor 600 also includes logic to implement store address prediction for memory disambiguation according to embodiments of the disclosure. In one embodiment, the execution block 611 of processor 600 may include a store address predictor (not shown) for implementing store address prediction for memory disambiguation.

The term “registers” may refer to the on-board processor storage locations that are used as part of instructions to identify operands. In other words, registers may be those that are usable from the outside of the processor (from a programmer's perspective). However, the registers of an embodiment should not be limited in meaning to a particular type of circuit. Rather, a register of an embodiment is capable of storing and providing data, and performing the functions described herein. The registers described herein can be implemented by circuitry within a processor using any number of different techniques, such as dedicated physical registers, dynamically allocated physical registers using register renaming, combinations of dedicated and dynamically allocated physical registers, etc. In one embodiment, integer registers store thirty-two bit integer data. A register file of one embodiment also contains eight multimedia SIMD registers for packed data.

For the discussions below, the registers are understood to be data registers designed to hold packed data, such as 64 bits wide MMX™ registers (also referred to as ‘mm’ registers in some instances) in microprocessors enabled with MMX technology from Intel Corporation of Santa Clara, Calif. These MMX registers, available in both integer and floating point forms, can operate with packed data elements that accompany SIMD and SSE instructions. Similarly, 128 bits wide XMM registers relating to SSE2, SSE3, SSE4, or beyond (referred to generically as “SSEx”) technology can also be used to hold such packed data operands. In one embodiment, in storing packed data and integer data, the registers do not need to differentiate between the two data types. In one embodiment, integer and floating point are either contained in the same register file or different register files. Furthermore, in one embodiment, floating point and integer data may be stored in different registers or the same registers.

Referring now to FIG. 7, shown is a block diagram illustrating a system 700 in which an embodiment of the disclosure may be used. As shown in FIG. 7, multiprocessor system 700 is a point-to-point interconnect system, and includes a first processor 770 and a second processor 780 coupled via a point-to-point interconnect 750. While shown with only two processors 770, 780, it is to be understood that the scope of embodiments of the disclosure is not so limited. In other embodiments, one or more additional processors may be present in a given processor. In one embodiment, the multiprocessor system 700 may implement hybrid cores as described herein.

Processors 770 and 780 are shown including integrated memory controller units 772 and 782, respectively. Processor 770 also includes as part of its bus controller units point-to-point (P-P) interfaces 776 and 778; similarly, second processor 780 includes P-P interfaces 786 and 788. Processors 770, 780 may exchange information via a point-to-point (P-P) interface 750 using P-P interface circuits 778, 788. As shown in FIG. 7, IMCs 772 and 782 couple the processors to respective memories, namely a memory 732 and a memory 734, which may be portions of main memory locally attached to the respective processors.

Processors 770, 780 may each exchange information with a chipset 790 via individual P-P interfaces 752, 754 using point to point interface circuits 776, 794, 786, 798. Chipset 790 may also exchange information with a high-performance graphics circuit 738 via a high-performance graphics interface 739.

A shared cache (not shown) may be included in either processor or outside of both processors, yet connected with the processors via P-P interconnect, such that either or both processors' local cache information may be stored in the shared cache if a processor is placed into a low power mode.

Chipset 790 may be coupled to a first bus 716 via an interface 796. In one embodiment, first bus 716 may be a Peripheral Component Interconnect (PCI) bus, or a bus such as a PCI Express bus or another third generation I/O interconnect bus, although the scope of the present disclosure is not so limited.

As shown in FIG. 7, various I/O devices 714 may be coupled to first bus 716, along with a bus bridge 718 which couples first bus 716 to a second bus 720. In one embodiment, second bus 720 may be a low pin count (LPC) bus. Various devices may be coupled to second bus 720 including, for example, a keyboard and/or mouse 722, communication devices 727 and a storage unit 728 such as a disk drive or other mass storage device which may include instructions/code and data 730, in one embodiment. Further, an audio I/O 724 may be coupled to second bus 720. Note that other architectures are possible. For example, instead of the point-to-point architecture of FIG. 7, a system may implement a multi-drop bus or other such architecture.

Referring now to FIG. 8, shown is a block diagram of a system 800 in which one embodiment of the disclosure may operate. The system 800 may include one or more processors 810, 815, which are coupled to graphics memory controller hub (GMCH) 820. The optional nature of additional processors 815 is denoted in FIG. 8 with broken lines. In one embodiment, processors 810, 815 implement hybrid cores according to embodiments of the disclosure.

Each processor 810, 815 may be some version of the circuit, integrated circuit, processor, and/or silicon integrated circuit as described above. However, it should be noted that it is unlikely that integrated graphics logic and integrated memory control units would exist in the processors 810, 815. FIG. 8 illustrates that the GMCH 820 may be coupled to a memory 840 that may be, for example, a dynamic random access memory (DRAM). The DRAM may, for at least one embodiment, be associated with a non-volatile cache.

The GMCH 820 may be a chipset, or a portion of a chipset. The GMCH 820 may communicate with the processor(s) 810, 815 and control interaction between the processor(s) 810, 815 and memory 840. The GMCH 820 may also act as an accelerated bus interface between the processor(s) 810, 815 and other elements of the system 800. For at least one embodiment, the GMCH 820 communicates with the processor(s) 810, 815 via a multi-drop bus, such as a frontside bus (FSB) 895.

Furthermore, GMCH 820 is coupled to a display 845 (such as a flat panel or touchscreen display). GMCH 820 may include an integrated graphics accelerator. GMCH 820 is further coupled to an input/output (I/O) controller hub (ICH) 850, which may be used to couple various peripheral devices to system 800. Shown for example in the embodiment of FIG. 8 is an external graphics device 860, which may be a discrete graphics device, coupled to ICH 850, along with another peripheral device 870.

Alternatively, additional or different processors may also be present in the system 800. For example, additional processor(s) 815 may include additional processors(s) that are the same as processor 810, additional processor(s) that are heterogeneous or asymmetric to processor 810, accelerators (such as, e.g., graphics accelerators or digital signal processing (DSP) units), field programmable gate arrays, or any other processor. There can be a variety of differences between the processor(s) 810, 815 in terms of a spectrum of metrics of merit including architectural, micro-architectural, thermal, power consumption characteristics, and the like. These differences may effectively manifest themselves as asymmetry and heterogeneity amongst the processors 810, 815. For at least one embodiment, the various processors 810, 815 may reside in the same die package.

Referring now to FIG. 9, shown is a block diagram of a system 900 in which an embodiment of the disclosure may operate. FIG. 9 illustrates processors 970, 980. In one embodiment, processors 970, 980 may implement hybrid cores as described above. Processors 970, 980 may include integrated memory and I/O control logic (“CL”) 972 and 982, respectively and intercommunicate with each other via point-to-point interconnect 950 between point-to-point (P-P) interfaces 978 and 988 respectively. Processors 970, 980 each communicate with chipset 990 via point-to-point interconnects 952 and 954 through the respective P-P interfaces 976 to 994 and 986 to 998 as shown. For at least one embodiment, the CL 972, 982 may include integrated memory controller units. CLs 972, 982 may include I/O control logic. As depicted, memories 932, 934 coupled to CLs 972, 982 and I/O devices 914 are also coupled to the control logic 972, 982. Legacy I/O devices 915 are coupled to the chipset 990 via interface 996.

Embodiments may be implemented in many different system types. FIG. 10 is a block diagram of a SoC 1000 in accordance with an embodiment of the present disclosure. Dashed lined boxes are optional features on more advanced SoCs. In FIG. 10, an interconnect unit(s) 1012 is coupled to: an application processor 1020 which includes a set of one or more cores 1002A-N and shared cache unit(s) 1006; a system agent unit 1010; a bus controller unit(s) 1016; an integrated memory controller unit(s) 1014; a set or one or more media processors 1018 which may include integrated graphics logic 1008, an image processor 1024 for providing still and/or video camera functionality, an audio processor 1026 for providing hardware audio acceleration, and a video processor 1028 for providing video encode/decode acceleration; an static random access memory (SRAM) unit 1030; a direct memory access (DMA) unit 1032; and a display unit 1040 for coupling to one or more external displays. In one embodiment, a memory module may be included in the integrated memory controller unit(s) 1014. In another embodiment, the memory module may be included in one or more other components of the SoC 1000 that may be used to access and/or control a memory. The application processor 1020 may include a store address predictor for implementing hybrid cores as described in embodiments herein.

The memory hierarchy includes one or more levels of cache within the cores, a set or one or more shared cache units 1006, and external memory (not shown) coupled to the set of integrated memory controller units 1014. The set of shared cache units 1006 may include one or more mid-level caches, such as level 2 (L2), level 3 (L3), level 4 (L4), or other levels of cache, a last level cache (LLC), and/or combinations thereof.

In some embodiments, one or more of the cores 1002A-N are capable of multi-threading. The system agent 1010 includes those components coordinating and operating cores 1002A-N. The system agent unit 1010 may include for example a power control unit (PCU) and a display unit. The PCU may be or include logic and components needed for regulating the power state of the cores 1002A-N and the integrated graphics logic 1008. The display unit is for driving one or more externally connected displays.

The cores 1002A-N may be homogenous or heterogeneous in terms of architecture and/or instruction set. For example, some of the cores 1002A-N may be in order while others are out-of-order. As another example, two or more of the cores 1002A-N may be capable of execution the same instruction set, while others may be capable of executing only a subset of that instruction set or a different instruction set.

The application processor 1020 may be a general-purpose processor, such as a Core™ i3, i5, i7, 2 Duo and Quad, Xeon™, Itanium™, Atom™ or Quark™ processor, which are available from Intel™ Corporation, of Santa Clara, Calif. Alternatively, the application processor 1020 may be from another company, such as ARM Holdings™, Ltd, MIPS™, etc. The application processor 1020 may be a special-purpose processor, such as, for example, a network or communication processor, compression engine, graphics processor, co-processor, embedded processor, or the like. The application processor 1020 may be implemented on one or more chips. The application processor 1020 may be a part of and/or may be implemented on one or more substrates using any of a number of process technologies, such as, for example, BiCMOS, CMOS, or NMOS.

FIG. 11 is a block diagram of an embodiment of a system on-chip (SoC) design in accordance with the present disclosure. As a specific illustrative example, SoC 1100 is included in user equipment (UE). In one embodiment, UE refers to any device to be used by an end-user to communicate, such as a hand-held phone, smartphone, tablet, ultra-thin notebook, notebook with broadband adapter, or any other similar communication device. Often a UE connects to a base station or node, which potentially corresponds in nature to a mobile station (MS) in a GSM network.

Here, SOC 1100 includes 2 cores—1106 and 1107. Cores 1106 and 1107 may conform to an Instruction Set Architecture, such as an Intel® Architecture Core™-based processor, an Advanced Micro Devices, Inc. (AMD) processor, a MIPS-based processor, an ARM-based processor design, or a customer thereof, as well as their licensees or adopters. Cores 1106 and 1107 are coupled to cache control 1108 that is associated with bus interface unit 1109 and L2 cache 1110 to communicate with other parts of system 1100. Interconnect 1110 includes an on-chip interconnect, such as an IOSF, AMBA, or other interconnect discussed above, which potentially implements one or more aspects of the described disclosure. In one embodiment, cores 1106, 1107 may implement hybrid cores as described in embodiments herein.

Interconnect 1110 provides communication channels to the other components, such as a Subscriber Identity Module (SIM) 1130 to interface with a SIM card, a boot ROM 1135 to hold boot code for execution by cores 1106 and 1107 to initialize and boot SoC 1100, a SDRAM controller 1140 to interface with external memory (e.g. DRAM 1160), a flash controller 1145 to interface with non-volatile memory (e.g. Flash 1165), a peripheral control 1150 (e.g. Serial Peripheral Interface) to interface with peripherals, video codecs 1120 and Video interface 1125 to display and receive input (e.g. touch enabled input), GPU 1115 to perform graphics related computations, etc. Any of these interfaces may incorporate aspects of the disclosure described herein. In addition, the system 1100 illustrates peripherals for communication, such as a Bluetooth module 1170, 3G modem 1175, GPS 1180, and Wi-Fi 1185.

FIG. 12 illustrates a diagrammatic representation of a machine in the example form of a computer system 1200 within which a set of instructions, for causing the machine to perform any one or more of the methodologies discussed herein, may be executed. In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, an intranet, an extranet, or the Internet. The machine may operate in the capacity of a server or a client device in a client-server network environment, or as a peer machine in a peer-to-peer (or distributed) network environment. The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a Personal Digital Assistant (PDA), a cellular telephone, a web appliance, a server, a network router, switch or bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by that machine. Further, while only a single machine is illustrated, the term “machine” shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

The computer system 1200 includes a processing device 1202, a main memory 1204 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) (such as synchronous DRAM (SDRAM) or DRAM (RDRAM), etc.), a static memory 1206 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage device 1218, which communicate with each other via a bus 1230.

Processing device 1202 represents one or more general-purpose processing devices such as a microprocessor, central processing unit, or the like. More particularly, the processing device may be complex instruction set computing (CISC) microprocessor, reduced instruction set computer (RISC) microprocessor, very long instruction word (VLIW) microprocessor, or processor implementing other instruction sets, or processors implementing a combination of instruction sets. Processing device 1202 may also be one or more special-purpose processing devices such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), network processor, or the like. In one embodiment, processing device 1202 may include one or processing cores. The processing device 1202 is configured to execute the processing logic 1226 for performing the operations and steps discussed herein. In one embodiment, processing device 1202 is the same as processor system 100 described with respect to FIG. 1A as described herein with embodiments of the disclosure.

The computer system 1200 may further include a network interface device 1208 communicably coupled to a network 1220. The computer system 1200 also may include a video display unit 1210 (e.g., a liquid crystal display (LCD) or a cathode ray tube (CRT)), an alphanumeric input device 1212 (e.g., a keyboard), a cursor control device 1214 (e.g., a mouse), and a signal generation device 1216 (e.g., a speaker). Furthermore, computer system 1200 may include a graphics processing unit 1222, a video processing unit 1228, and an audio processing unit 1232.

The data storage device 1218 may include a machine-accessible storage medium 1224 on which is stored software 1226 implementing any one or more of the methodologies of functions described herein, such as implementing store address prediction for memory disambiguation as described above. The software 1226 may also reside, completely or at least partially, within the main memory 1204 as instructions 1226 and/or within the processing device 1202 as processing logic 1226 during execution thereof by the computer system 1200; the main memory 1204 and the processing device 1202 also constituting machine-accessible storage media.

The machine-readable storage medium 1224 may also be used to store instructions 1226 implementing store address prediction for hybrid cores such as described according to embodiments of the disclosure. While the machine-accessible storage medium 1128 is shown in an example embodiment to be a single medium, the term “machine-accessible storage medium” should be taken to include a single medium or multiple media (e.g., a centralized or distributed database, and/or associated caches and servers) that store the one or more sets of instructions. The term “machine-accessible storage medium” shall also be taken to include any medium that is capable of storing, encoding or carrying a set of instruction for execution by the machine and that cause the machine to perform any one or more of the methodologies of the present disclosure. The term “machine-accessible storage medium” shall accordingly be taken to include, but not be limited to, solid-state memories, and optical and magnetic media.

The following examples pertain to further embodiments.

Example 1 is a processor including: (1) a processing core to execute a transaction with a memory via a cache; and (2) a cache controller coupled to the processing core, the cache controller comprising an index mapper circuit to: a) identify a physical memory address associated with the transaction, wherein the physical memory address comprises a plurality of bits; b) determine, based on the plurality of bits, a first set of bits encoding a tag value corresponding to a first memory address group, a second set of bits encoding a page index value corresponding to a page of the first memory address group, and a third set of bits encoding a line index value corresponding to a line of the page; c) determine a mapping function corresponding to the tag value; d) determine, using the mapping function, a bit-placement order for combining the second set of bits and the third set of bits; e) form an index for the cache via combination, based on the bit-placement order, of the second set of bits and the third set of bits; and f) generate, using the index, a mapping from the physical memory address to a cache line index value identifying a cache line in the cache; and g) wherein the cache controller is further to access, using the mapping and in response to the transaction containing the physical memory address, the cache line in the cache.

In Example 2, the processor of Example 1, wherein the cache is a direct mapped cache, and wherein each cache line in the direct mapped cache is identified by a respective cache line index value.

In Example 3, the processor of Example 1, wherein the cache is at least one of a memory-side cache or a last-level cache (LLC).

In Example 4, the processor of Example 1, wherein to combine the second set of bits and the third set of bits, the index mapper circuit is to swap at least one bit of the second set of bits with at least one bit of the third set of bits.

In Example 5, the processor of Example 4, wherein the index mapper circuit further comprises at least one multiplexer circuit comprising: 1) a first input node to receive the at least one bit of the second set of bits; 2) a second input node to receive the at least one bit of the third set of bits; and 3) a control node to receive the tag value, wherein the at least one multiplexer is to, using the tag value, swap the at least one bit of the second set of bits with the at least one bit of the third set of bits.

In Example 6, the processor of Example 1, further comprising 1) a memory controller coupled to the processing core, the memory controller to at least one of read from or write to, via the cache line, a memory location referenced by the physical memory address.

In Example 7, the processor of Example 1, wherein the index mapper circuit is further to: a) determine a second mapping function corresponding to a second tag value of a second physical memory address received in a second transaction, the second physical memory address also including a second page index value and a second line index value; and b) convert, via application of the second mapping function to the second page index value and the second line index value, the second physical memory address to a second cache line index value that is different from the second cache line index value.

In Example 8, the processor of Example 7, wherein the second mapping function comprises a second bit-placement order, corresponding to the second tag value, for combining the second set of bits and the third set of bits of the second physical memory address.

Example 9 is a system including: 1) a memory; and 2) a processor coupled to the memory, the processor including: 3) a cache; 4) a processing core to execute a transaction with the memory via the cache; and 5) a cache controller coupled to the cache and the processing core, the cache controller comprising an index mapper circuit to: a) identify a physical memory address associated with the transaction, wherein the physical memory address comprises a plurality of bits; b) determine, based on the plurality of bits, a first set of bits encoding a tag value corresponding to a first memory address group, a second set of bits encoding a page index value corresponding to a page of the first memory address group, and a third set of bits encoding a line index value corresponding to a line of the page; c) determine a mapping function corresponding to the tag value; d) determine, using the mapping function, a bit-placement order for combining the second set of bits and the third set of bits; e) form an index for the cache via combination, based on the bit-placement order, of the second set of bits and the third set of bits; and f) generate, using the index, a mapping from the physical memory address to a cache line index value identifying a cache line in the cache; and g) wherein the cache controller is further to access, using the mapping and in response to the transaction containing the physical memory address, the cache line in the cache.

In Example 10, the system of Example 9, wherein the cache is a direct mapped cache, and wherein each cache line in the direct mapped cache is identified by a respective cache line index value.

In Example 11, the system of Example 9, wherein the cache is at least one of a memory-side cache or a last-level cache (LLC).

In Example 12, the system of Example 9, wherein to combine the second set of bits and the third set of bits, the index mapper circuit is to swap at least one bit of the second set of bits with at least one bit of the third set of bits.

In Example 13, the system of Example 12, wherein the index mapper circuit further comprises at least one multiplexer circuit comprising: 1) a first input node to receive the at least one bit of the second set of bits; 2) a second input node to receive the at least one bit of the third set of bits; and 3) a control node to receive the tag value, wherein the at least one multiplexer is to, using the tag value, swap the at least one bit of the second set of bits with the at least one bit of the third set of bits.

In Example 14, the system of Example 9, wherein the processor further comprises a memory controller coupled to the processing core, the memory controller to at least one of read from or write to, via the cache line, a memory location referenced by the physical memory address.

In Example 15, the system of Example 9, wherein the index mapper circuit is further to: a) determine a second mapping function corresponding to a second tag value of a second physical memory address received in a second transaction, the second physical memory address also including a second page index value and a second line index value; and b) convert, via application of the second mapping function to the second page index value and the second line index value, the second physical memory address to a second cache line index value that is different from the second cache line index value.

In Example 16, the system of Example 15, wherein the second mapping function comprises a second bit-placement order, corresponding to the second tag value, for combining the second set of bits and the third set of bits of the second physical memory address.

Example 17 is a method including: a) identifying, by a processor containing cache to be mapped to memory, a physical memory address of a memory page, wherein the physical memory address comprises a plurality of bits; b) determining, based on the plurality of bits, a first set of bits encoding a tag value corresponding to a first memory address group, a second set of bits encoding a page index value corresponding to a page of the first memory address group, and a third set of bits encoding a line index value corresponding to a line of the page; c) determining a mapping function corresponding to the tag value; d) determining, using the mapping function, a bit-placement order for combining the second set of bits and the third set of bits; e) forming an index for the cache via combining, based on the bit-placement order, of the second set of bits and the third set of bits; f) generating, using the index, a mapping from the physical memory address to a cache line index value identifying a cache line in the cache; and g) accessing, using the mapping and in response to a transaction containing the physical memory address, the cache line in the cache.

In Example 18, the method of Example 17, wherein the cache is a direct mapped cache, and wherein each cache line in the direct mapped cache is identified by a respective cache line index value.

In Example 19, the method of Example 17, further including: a) determining a second mapping function corresponding to a second tag value of a second physical memory address received in a second transaction, the second physical memory address also including a second page index value and a second line index value; and b) converting, via application of the second mapping function to the second page index value and the second line index value, the second physical memory address to a second cache line index value that is different from the second cache line index value.

In Example 20, the method of Example 19, wherein the second mapping function includes a second bit-placement order, corresponding to the second tag value, for combining the second set of bits and the third set of bits of the second physical memory address.

Example 21 is an apparatus comprising: means for performing the method of any of Examples 17 through 20.

Example 22 is a machine-readable non-transitory medium having stored thereon program code that, when executed, perform operations including: a) identifying, by a processor containing cache to be mapped to memory, a physical memory address of a memory page, wherein the physical memory address comprises a plurality of bits; b) determining, based on the plurality of bits, a first set of bits encoding a tag value corresponding to a first memory address group, a second set of bits encoding a page index value corresponding to a page of the first memory address group, and a third set of bits encoding a line index value corresponding to a line of the page; c) determining a mapping function corresponding to the tag value; d) determining, using the mapping function, a bit-placement order for combining the second set of bits and the third set of bits; e) forming an index for the cache via combining, based on the bit-placement order, of the second set of bits and the third set of bits; f) generating, using the index, a mapping from the physical memory address to a cache line index value identifying a cache line in the cache; and g) accessing, using the mapping and in response to a transaction containing the physical memory address, the cache line in the cache.

In Example 23, the machine-readable non-transitory medium of Example 22, wherein the cache is a direct mapped cache, and wherein each cache line in the direct mapped cache is identified by a respective cache line index value.

In Example 24, the machine-readable non-transitory medium of Example 22, wherein the operations further including: a) determining a second mapping function corresponding to a second tag value of a second physical memory address received in a second transaction, the second physical memory address also including a second page index value and a second line index value; and b) converting, via application of the second mapping function to the second page index value and the second line index value, the second physical memory address to a second cache line index value that is different from the second cache line index value.

In Example 25, the machine-readable non-transitory medium of Example 24, wherein the second mapping function includes a second bit-placement order, corresponding to the second tag value, for combining the second set of bits and the third set of bits of the second physical memory address.

While the disclosure has been described with respect to a limited number of embodiments, those skilled in the art will appreciate numerous modifications and variations there from. It is intended that the appended claims cover all such modifications and variations as fall within the true spirit and scope of this disclosure.

A design may go through various stages, from creation to simulation to fabrication. Data representing a design may represent the design in a number of manners. First, as is useful in simulations, the hardware may be represented using a hardware description language or another functional description language. Additionally, a circuit level model with logic and/or transistor gates may be produced at some stages of the design process. Furthermore, most designs, at some stage, reach a level of data representing the physical placement of various devices in the hardware model. In the case where conventional semiconductor fabrication techniques are used, the data representing the hardware model may be the data specifying the presence or absence of various features on different mask layers for masks used to produce the integrated circuit. In any representation of the design, the data may be stored in any form of a machine readable medium. A memory or a magnetic or optical storage such as a disc may be the machine readable medium to store information transmitted via optical or electrical wave modulated or otherwise generated to transmit such information. When an electrical carrier wave indicating or carrying the code or design is transmitted, to the extent that copying, buffering, or re-transmission of the electrical signal is performed, a new copy is made. Thus, a communication provider or a network provider may store on a tangible, machine-readable medium, at least temporarily, an article, such as information encoded into a carrier wave, embodying techniques of embodiments of the present disclosure.

A module as used herein refers to any combination of hardware, software, and/or firmware. As an example, a module includes hardware, such as a micro-controller, associated with a non-transitory medium to store code adapted to be executed by the micro-controller. Therefore, reference to a module, in one embodiment, refers to the hardware, which is specifically configured to recognize and/or execute the code to be held on a non-transitory medium. Furthermore, in another embodiment, use of a module refers to the non-transitory medium including the code, which is specifically adapted to be executed by the microcontroller to perform predetermined operations. And as can be inferred, in yet another embodiment, the term module (in this example) may refer to the combination of the microcontroller and the non-transitory medium. Often module boundaries that are illustrated as separate commonly vary and potentially overlap. For example, a first and a second module may share hardware, software, firmware, or a combination thereof, while potentially retaining some independent hardware, software, or firmware. In one embodiment, use of the term logic includes hardware, such as transistors, registers, or other hardware, such as programmable logic devices.

Use of the phrase ‘configured to,’ in one embodiment, refers to arranging, putting together, manufacturing, offering to sell, importing and/or designing an apparatus, hardware, logic, or element to perform a designated or determined task. In this example, an apparatus or element thereof that is not operating is still ‘configured to’ perform a designated task if it is designed, coupled, and/or interconnected to perform said designated task. As a purely illustrative example, a logic gate may provide a 0 or a 1 during operation. But a logic gate ‘configured to’ provide an enable signal to a clock does not include every potential logic gate that may provide a 1 or 0. Instead, the logic gate is one coupled in some manner that during operation the 1 or 0 output is to enable the clock. Note once again that use of the term ‘configured to’ does not require operation, but instead focus on the latent state of an apparatus, hardware, and/or element, where in the latent state the apparatus, hardware, and/or element is designed to perform a particular task when the apparatus, hardware, and/or element is operating.

Furthermore, use of the phrases ‘to,’ ‘capable of/to,’ and or ‘operable to,’ in one embodiment, refers to some apparatus, logic, hardware, and/or element designed in such a way to enable use of the apparatus, logic, hardware, and/or element in a specified manner. Note as above that use of to, capable to, or operable to, in one embodiment, refers to the latent state of an apparatus, logic, hardware, and/or element, where the apparatus, logic, hardware, and/or element is not operating but is designed in such a manner to enable use of an apparatus in a specified manner.

A value, as used herein, includes any known representation of a number, a state, a logical state, or a binary logical state. Often, the use of logic levels, logic values, or logical values is also referred to as l's and 0's, which simply represents binary logic states. For example, a 1 refers to a high logic level and 0 refers to a low logic level. In one embodiment, a storage cell, such as a transistor or flash cell, may be capable of holding a single logical value or multiple logical values. However, other representations of values in computer systems have been used. For example the decimal number ten may also be represented as a binary value of 910 and a hexadecimal letter A. Therefore, a value includes any representation of information capable of being held in a computer system.

Moreover, states may be represented by values or portions of values. As an example, a first value, such as a logical one, may represent a default or initial state, while a second value, such as a logical zero, may represent a non-default state. In addition, the terms reset and set, in one embodiment, refer to a default and an updated value or state, respectively. For example, a default value potentially includes a high logical value, i.e. reset, while an updated value potentially includes a low logical value, i.e. set. Note that any combination of values may be utilized to represent any number of states.

The embodiments of methods, hardware, software, firmware or code set forth above may be implemented via instructions or code stored on a machine-accessible, machine readable, computer accessible, or computer readable medium which are executable by a processing element. A non-transitory machine-accessible/readable medium includes any mechanism that provides (i.e., stores and/or transmits) information in a form readable by a machine, such as a computer or electronic system. For example, a non-transitory machine-accessible medium includes random-access memory (RAM), such as static RAM (SRAM) or dynamic RAM (DRAM); ROM; magnetic or optical storage medium; flash memory devices; electrical storage devices; optical storage devices; acoustical storage devices; other form of storage devices for holding information received from transitory (propagated) signals (e.g., carrier waves, infrared signals, digital signals); etc., which are to be distinguished from the non-transitory mediums that may receive information there from.

Instructions used to program logic to perform embodiments of the disclosure may be stored within a memory in the system, such as DRAM, cache, flash memory, or other storage. Furthermore, the instructions can be distributed via a network or by way of other computer readable media. Thus a machine-readable medium may include any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer), but is not limited to, floppy diskettes, optical disks, Compact Disc, Read-Only Memory (CD-ROMs), and magneto-optical disks, Read-Only Memory (ROMs), Random Access Memory (RAM), Erasable Programmable Read-Only Memory (EPROM), Electrically Erasable Programmable Read-Only Memory (EEPROM), magnetic or optical cards, flash memory, or a tangible, machine-readable storage used in the transmission of information over the Internet via electrical, optical, acoustical or other forms of propagated signals (e.g., carrier waves, infrared signals, digital signals, etc.). Accordingly, the computer-readable medium includes any type of tangible machine-readable medium suitable for storing or transmitting electronic instructions or information in a form readable by a machine (e.g., a computer).

Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, the appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

In the foregoing specification, a detailed description has been given with reference to specific exemplary embodiments. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the disclosure as set forth in the appended claims. The specification and drawings are, accordingly, to be regarded in an illustrative sense rather than a restrictive sense. Furthermore, the foregoing use of embodiment and other exemplarily language does not necessarily refer to the same embodiment or the same example, but may refer to different and distinct embodiments, as well as potentially the same embodiment. 

What is claimed is:
 1. A processor comprising: a processing core to execute a transaction with a memory via a cache; and a cache controller coupled to the processing core, the cache controller comprising an index mapper circuit to: identify a physical memory address associated with the transaction, wherein the physical memory address comprises a plurality of bits; determine, based on the plurality of bits, a first set of bits encoding a tag value corresponding to a first memory address group, a second set of bits encoding a page index value corresponding to a page of the first memory address group, and a third set of bits encoding a line index value corresponding to a line of the page; determine a mapping function corresponding to the tag value; determine, using the mapping function, a bit-placement order for combining the second set of bits and the third set of bits; form an index for the cache via combination, based on the bit-placement order, of the second set of bits and the third set of bits; and generate, using the index, a mapping from the physical memory address to a cache line index value identifying a cache line in the cache; and wherein the cache controller is further to access, using the mapping and in response to the transaction containing the physical memory address, the cache line in the cache.
 2. The processor of claim 1, wherein the cache is a direct mapped cache, and wherein each cache line in the direct mapped cache is identified by a respective cache line index value.
 3. The processor of claim 1, wherein the cache is at least one of a memory-side cache or a last-level cache (LLC).
 4. The processor of claim 1, wherein to combine the second set of bits and the third set of bits, the index mapper circuit is to swap at least one bit of the second set of bits with at least one bit of the third set of bits.
 5. The processor of claim 4, wherein the index mapper circuit further comprises at least one multiplexer circuit comprising: a first input node to receive the at least one bit of the second set of bits; a second input node to receive the at least one bit of the third set of bits; and a control node to receive the tag value, wherein the at least one multiplexer is to, using the tag value, swap the at least one bit of the second set of bits with the at least one bit of the third set of bits.
 6. The processor of claim 1, further comprising a memory controller coupled to the processing core, the memory controller to at least one of read from or write to, via the cache line, a memory location referenced by the physical memory address.
 7. The processor of claim 1, wherein the index mapper circuit is further to: determine a second mapping function corresponding to a second tag value of a second physical memory address received in a second transaction, the second physical memory address also including a second page index value and a second line index value; and convert, via application of the second mapping function to the second page index value and the second line index value, the second physical memory address to a second cache line index value that is different from the second cache line index value.
 8. The processor of claim 7, wherein the second mapping function comprises a second bit-placement order, corresponding to the second tag value, for combining the second set of bits and the third set of bits of the second physical memory address.
 9. A system comprising: a memory; and a processor coupled to the memory, the processor comprising: a cache; a processing core to execute a transaction with the memory via the cache; and a cache controller coupled to the cache and the processing core, the cache controller comprising an index mapper circuit to: identify a physical memory address associated with the transaction, wherein the physical memory address comprises a plurality of bits; determine, based on the plurality of bits, a first set of bits encoding a tag value corresponding to a first memory address group, a second set of bits encoding a page index value corresponding to a page of the first memory address group, and a third set of bits encoding a line index value corresponding to a line of the page; determine a mapping function corresponding to the tag value; determine, using the mapping function, a bit-placement order for combining the second set of bits and the third set of bits; form an index for the cache via combination, based on the bit-placement order, of the second set of bits and the third set of bits; and generate, using the index, a mapping from the physical memory address to a cache line index value identifying a cache line in the cache; and wherein the cache controller is further to access, using the mapping and in response to the transaction containing the physical memory address, the cache line in the cache.
 10. The system of claim 9, wherein the cache is a direct mapped cache, and wherein each cache line in the direct mapped cache is identified by a respective cache line index value.
 11. The system of claim 9, wherein the cache is at least one of a memory-side cache or a last-level cache (LLC).
 12. The system of claim 9, wherein to combine the second set of bits and the third set of bits, the index mapper circuit is to swap at least one bit of the second set of bits with at least one bit of the third set of bits.
 13. The system of claim 12, wherein the index mapper circuit further comprises at least one multiplexer circuit comprising: a first input node to receive the at least one bit of the second set of bits; a second input node to receive the at least one bit of the third set of bits; and a control node to receive the tag value, wherein the at least one multiplexer is to, using the tag value, swap the at least one bit of the second set of bits with the at least one bit of the third set of bits.
 14. The system of claim 9, wherein the processor further comprises a memory controller coupled to the processing core, the memory controller to at least one of read from or write to, via the cache line, a memory location referenced by the physical memory address.
 15. The system of claim 9, wherein the index mapper circuit is further to: determine a second mapping function corresponding to a second tag value of a second physical memory address received in a second transaction, the second physical memory address also including a second page index value and a second line index value; and convert, via application of the second mapping function to the second page index value and the second line index value, the second physical memory address to a second cache line index value that is different from the second cache line index value.
 16. The system of claim 15, wherein the second mapping function comprises a second bit-placement order, corresponding to the second tag value, for combining the second set of bits and the third set of bits of the second physical memory address.
 17. A method comprising: identifying, by a processor containing cache to be mapped to memory, a physical memory address of a memory page, wherein the physical memory address comprises a plurality of bits; determining, based on the plurality of bits, a first set of bits encoding a tag value corresponding to a first memory address group, a second set of bits encoding a page index value corresponding to a page of the first memory address group, and a third set of bits encoding a line index value corresponding to a line of the page; determining a mapping function corresponding to the tag value; determining, using the mapping function, a bit-placement order for combining the second set of bits and the third set of bits; forming an index for the cache via combining, based on the bit-placement order, of the second set of bits and the third set of bits; generating, using the index, a mapping from the physical memory address to a cache line index value identifying a cache line in the cache; and accessing, using the mapping and in response to a transaction containing the physical memory address, the cache line in the cache.
 18. The method of claim 17, wherein the cache is a direct mapped cache, and wherein each cache line in the direct mapped cache is identified by a respective cache line index value.
 19. The method of claim 17, further comprising: determining a second mapping function corresponding to a second tag value of a second physical memory address received in a second transaction, the second physical memory address also including a second page index value and a second line index value; and converting, via application of the second mapping function to the second page index value and the second line index value, the second physical memory address to a second cache line index value that is different from the second cache line index value.
 20. The method of claim 19, wherein the second mapping function comprises a second bit-placement order, corresponding to the second tag value, for combining the second set of bits and the third set of bits of the second physical memory address. 